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2005 Microchip Technology Inc.
Preliminary
DS41265A-page 265
PIC16F946
R
R/W bit .............................................................................. 166
RCSTA Register
ADDEN Bit ................................................................ 134
CREN Bit................................................................... 134
FERR Bit ................................................................... 134
OERR Bit .................................................................. 134
RX9 Bit...................................................................... 134
RX9D Bit ................................................................... 134
SPEN Bit ........................................................... 133, 134
SREN Bit................................................................... 134
Reader Response ............................................................. 270
Read-Modify-Write Operations ......................................... 213
Receive Overflow Indicator bit (SSPOV) .......................... 167
Registers
ADCON0 (A/D Control 0) .......................................... 152
ADCON1 (A/D Control 1) .......................................... 153
ANSEL (Analog Select)............................................. 152
CCP1CON (CCP Control 2)...................................... 184
CCP2CON (CCP Control 1)...................................... 184
CMCON0 (Comparator Control 0) .............................. 95
CMCON1 (Comparator Control 1) .............................. 99
CONFIG (Configuration Word).................................. 192
EEADRH (EEPROM Address).................................. 160
EEADRL (EEPROM Address) .................................. 160
EECON1 (EEPROM Control 1)................................. 161
EEDATH (EEPROM Data)........................................ 160
EEDATL (EEPROM Data) ........................................ 160
INTCON (Interrupt Control)......................................... 19
IOCB (PORTB Interrupt-on-change)........................... 38
LCDCON (LCD Control)............................................ 105
LCDDATAx (LCD Datax) .......................................... 107
LCDPS (LCD Prescaler Select) ................................ 106
LCDSEn (LCD Segment) .......................................... 107
LVDCON (Low-Voltage Detect Control).................... 131
OPTION_REG ...................................................... 18, 84
OSCCON (Oscillator Control) ..................................... 72
OSCTUNE .................................................................. 78
PCON (Power Control) ............................................. 196
PIE1 (Peripheral Interrupt Enable 1)........................... 20
PIE2 (Peripheral Interrupt Enable 2)........................... 21
PIR1 (Peripheral Interrupt Register 1) ........................ 22
PIR2 (Peripheral Interrupt Register 2) ........................ 23
PORTA........................................................................ 28
PORTB........................................................................ 38
PORTC ....................................................................... 47
PORTD ....................................................................... 56
PORTE........................................................................ 61
PORTF........................................................................ 65
PORTG ....................................................................... 68
RCSTA (Receive Status and Control)....................... 134
Reset Values............................................................. 198
Reset Values (Special Registers) ............................. 201
Special Function Register Map
PIC16F946.......................................................... 12
Special Register Summary
Bank 0................................................................. 13
Bank 1................................................................. 14
Bank 2................................................................. 15
Bank 3................................................................. 16
SSPCON (Sync Serial Port Control) Register........... 167
SSPSTAT (Sync Serial Port Status) Register........... 166
Status.......................................................................... 17
T1CON (Timer1 Control)............................................. 89
T2CON (Timer2 Control)............................................. 93
TRISA (PORTA Tri-state) ........................................... 28
TRISB (PORTB Tri-state) ........................................... 38
TRISC (PORTC Tri-state)........................................... 47
TRISD (PORTD Tri-state)........................................... 56
TRISE (PORTE Tri-state) ........................................... 61
TRISF (PORTF Tri-state) ........................................... 65
TRISG (PORTG Tri-state) .......................................... 68
TXSTA (Transmit Status and Control)...................... 133
VRCON (Voltage Reference Control) ....................... 102
WDTCON (Watchdog Timer Control) ....................... 207
WPUB (Weak Pull-up PORTB)................................... 39
Reset ................................................................................ 193
Revision History................................................................ 259
S
S (Start) bit ....................................................................... 166
SCI. See USART
Serial Communication Interface. See USART.
Slave Select Synchronization ........................................... 172
SMP bit ............................................................................. 166
Software Simulator (MPLAB SIM) .................................... 224
Software Simulator (MPLAB SIM30) ................................ 224
Special Function Registers ................................................. 11
SPI Mode .................................................................. 165, 172
Associated Registers................................................ 174
Bus Mode Compatibility ............................................ 174
Effects of a Reset ..................................................... 174
Enabling SPI I/O ....................................................... 170
Master Mode............................................................. 171
Master/Slave Connection ......................................... 170
Serial Clock (SCK pin) .............................................. 165
Serial Data In (SDI pin)............................................. 165
Serial Data Out (SDO pin) ........................................ 165
Slave Select.............................................................. 165
Slave Select Synchronization ................................... 172
Sleep Operation........................................................ 174
SPI Clock.................................................................. 171
Typical Connection ................................................... 170
SSP
Overview
SPI Master/Slave Connection................................... 170
SSP I2C Operation ........................................................... 175
Slave Mode............................................................... 175
SSP Module
Clock Synchronization and the CKP Bit ................... 181
SPI Master Mode...................................................... 171
SPI Slave Mode........................................................ 172
SSPBUF ................................................................... 171
SSPSR ..................................................................... 171
SSPEN bit......................................................................... 167
SSPM bits ......................................................................... 167
SSPOV bit ........................................................................ 167
Status Register ................................................................... 17
Synchronous Master Reception
Associated Registers................................................ 146
Synchronous Master Transmission
Associated Registers................................................ 145
Synchronous Serial Port Enable bit (SSPEN) .................. 167
Synchronous Serial Port Mode Select bits (SSPM).......... 167
Synchronous Serial Port. See SSP
Synchronous Slave Reception
Associated Registers................................................ 148
Synchronous Slave Transmission
Associated Registers................................................ 148
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